Semiconductor integrated circuit, operating method thereof, and IC card including the circuit

ABSTRACT

One main electrode of a TFT is connected with one terminal of a two-terminal type nonvolatile memory element, a gate electrode of the TFT is connected with a word line, and the other main electrode thereof is connected with a bit line. The other terminal of the memory element is connected with a base line. A fixed resistor is connected between a connecting point between the other main electrode of the TFT and the bit line and an input terminal of the bit line. In information writing for changing the memory element whose initial state is a low impedance state to a high impedance state, voltages having polarities reverse relative to a reference voltage are applied to the input terminal of the bit line and an input terminal of the base line, respectively, so that a high voltage necessary to change the state is applied between both the terminals of the memory element.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitwhich is a nonvolatile memory in which information is retained evenafter a power source is turned off, an operating method thereof, and anIC card including the semiconductor integrated circuit.

BACKGROUND ART

In a semiconductor field, up to now, a system constructed using singlecrystalline silicon has been general. In recent years, development ofelements and circuits using non-crystalline silicon such as amorphoussilicon or polycrystalline silicon or a non-silicon semiconductor suchas an organic semiconductor, diamond, or silicon carbide has beenprogressing rapidly.

However, the single crystalline silicon constituting an element has asuperior characteristic. Therefore, the large majority of semiconductorintegrated circuits which are actually used are fundamentally made of asingle crystalline silicon. Circuits each using a semiconductor otherthan the single crystalline silicon have not been studied sufficientlyup to now.

A semiconductor memory which is a principal constituent circuit of acomputer has not been also studied. In particular, in a nonvolatilememory in which information is retained even after a power source isturned off, a single crystalline silicon transistor is used as atransistor for controlling an applied voltage to a memory element(Japanese Patent Application Laid-Open No. 2002-530850).

DISCLOSURE OF THE INVENTION

In general, the single crystalline silicon transistor is manufactured byusing a single crystalline silicon substrate (wafer) and it is hard toform the transistor in a substrate other than the single crystallinesilicon substrate. On the other hand, it is possible to form atransistor using the non-crystalline silicon or the non-siliconsemiconductor in the substrate other than the single crystalline siliconsubstrate, such as a glass substrate or a resin substrate. Therefore, ifa circuit can be constructed by using the semiconductor other than thesingle crystalline silicon, there is a wide choice of substrates. Thus,it is expected to rapidly expand applications of the circuit.

However, when a circuit is constructed by using a transistor made of thesemiconductor other than the single crystalline silicon, which has notbeen studied up to now, in particular, a thin film transistor, in theabove-mentioned nonvolatile memory, there is a problem in that asufficient voltage cannot be applied to a memory element at a time wheninformation is written into the memory element because the transistorhas a high on-resistance.

An object of the present invention is to provide a semiconductorintegrated circuit which can preferably operate even when a transistorhaving a high on-resistance other than the single crystalline silicontransistor is used for the nonvolatile memory and an operating methodthereof, and further to provide an IC card using the semiconductorintegrated circuit.

According to a first aspect of the present invention, there is provideda semiconductor integrated circuit including:

a plurality of memory cells, each of which includes a field effecttransistor having a gate electrode, two main electrodes, and asemiconductor layer and a two-terminal type nonvolatile memory element,in which one of the main electrodes of the transistor is connected withone terminal of the nonvolatile memory element, the other mainelectrodes are connected with a bit line, the gate electrode isconnected with a word line, and the other terminal of the memory elementis connected with a base line;

means for detecting a potential on a connecting portion between the bitline and the other main electrodes of the transistor; and

means capable of supplying voltages having polarities reverse relativeto a reference voltage to an input terminal of the bit line and an inputterminal of the base line, respectively.

In further aspect of the semiconductor integrated circuit, it ispreferable that:

the field effect transistor does not contain single crystalline silicon;

the field effect transistor is a thin film transistor;

the field effect transistor is made of non-crystalline silicon or anorganic semiconductor;

the nonvolatile memory element shows a high impedance state and a lowimpedance state; and

the nonvolatile memory element is made of a material containing organicmatter.

According to a second aspect of the present invention, there is provideda method of operating a semiconductor integrated circuit including aplurality of memory cells, each of which includes a field effecttransistor having a gate electrode, two main electrodes, and asemiconductor layer and a two-terminal type nonvolatile memory element,in which one of the main electrodes of the transistor is connected withone terminal of the nonvolatile memory element, the other mainelectrodes are connected with a bit line, the gate electrode isconnected with a word line, and the other terminal of the memory elementis connected with a base line; and means for detecting a potential on aconnecting portion between the bit line and the other main electrodes ofthe transistor, the method including:

supplying voltages having polarities reverse relative to a referencevoltage to an input terminal of the bit line and an input terminal ofthe base line, respectively to apply a predetermined voltage betweenboth the terminals of the memory element.

In further aspect of the method of operating a semiconductor integratedcircuit, it is preferable that:

a predetermined voltage is applied between both the terminals of thememory element to write information in the memory element by supplyingthe voltages having the polarities reverse relative to the referencevoltage to the input terminal of the bit line and the input terminal ofthe base line, respectively;

the nonvolatile memory element is a rewritable memory element, and apredetermined voltage is applied between both the terminals of thememory element to write information therein by supplying the voltageshaving the polarities reverse relative to the reference voltage to theinput terminal of the bit line and the input terminal of the base line,respectively; and

a predetermined voltage having a polarity reverse to that at writing isapplied between both the terminals of the memory element to erase theinformation written in the memory element by supplying voltages havingpolarities reverse to those at the writing to the input terminal of thebit line and the input terminal of the base line, respectively.

According to a third aspect of the present invention, there is providedan IC card including the above semiconductor integrated circuit.

According to the present invention, it is possible to use a transistormade of a semiconductor other than the single crystalline silicon.Therefore, the nonvolatile memory can be provided at lower cost by massproduction by using the transistor.

The transistor made of the semiconductor other than the singlecrystalline silicon can be formed on the substrate other than the singlecrystalline silicon substrate, such as a glass substrate, a plasticsubstrate, or a paper, so that applications rapidly expand. Inparticular, the semiconductor integrated circuit of the presentinvention is preferably applied to an IC card. Therefore, it is alsopossible to construct a flexible IC card by using, for example, aflexible substrate. In addition, the IC card is writable and rewritable,with the result that historical information of products can be inputtedfor control with time by application to, for example, a tag for productcontrol.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an equivalent circuit diagram showing a memory cell of asemiconductor integrated circuit according to an embodiment of thepresent invention.

FIG. 2 is a graph showing an electrical characteristic of a memoryelement used in the present invention.

FIGS. 3A, 3B, 3C, 3D, 3E, and 3F are timing charts at the time ofoperation of the memory cell shown in FIG. 1.

FIG. 4 is an equivalent circuit diagram showing the semiconductorintegrated circuit according to the embodiment of the present invention.

FIG. 5 is an equivalent circuit diagram showing a memory cell of asemiconductor integrated circuit according to another embodiment of thepresent invention.

FIGS. 6A, 6B and 6C are timing charts at the time of erase operation ofthe memory cell shown in FIG. 5.

BEST MODES FOR CARRYING OUT THE INVENTION

A semiconductor integrated circuit of the present invention is anonvolatile memory which is characterized by including a plurality ofmemory cells, each of which has a field effect transistor (FET) and atwo-terminal type memory element, and the circuit is characterized inthat a sufficiently high voltage is applied by supplying voltages havingpolarities reverse to each other between both terminals of the memorycell at a time when a predetermined voltage is applied between both theterminals.

The FET used in the present invention has a gate electrode, two mainelectrodes, and a semiconductor layer. Any of single crystallinesilicon, polycrystalline silicon, non-crystalline silicon such asamorphous silicon, and a non-silicon organic semiconductor can be usedfor the semiconductor layer. It is also possible to use a thin filmtransistor (TFT). Any of the non-crystalline silicon and the organicsemiconductor is preferably used for a semiconductor layer of the TFT.Any type of a p-channel type and an n-channel type can be used.

A nonvolatile memory element used in the present invention is preferablya memory cell which can retain temporarily written information for along period after a power source is turned off and preferably has twostates which are a high impedance state and a low impedance state. Insuch a memory element, for example, “1” and “0” are assigned to the twostates, respectively, so that the memory element can be operated as thenonvolatile memory element.

The nonvolatile memory element has an irreversible type in whichtemporarily written information cannot be rewritten and a reversibletype (rewritable) in which temporarily written information can berewritten. The former includes a fuse type and an anti-fuse type and thelatter includes a rewritable type element containing organic matter. Inparticular, the present invention is characterized in that voltageshaving polarities reverse to each other are applied between bothterminals of the memory element at a time when any information of “0”and “1” is written in information write operation. In the case where thememory element is of the reversible type, voltages having polaritiesreverse to each other are applied between both the terminals of thememory element at a time when any information of “0” and “1” is writtenin information write operation. In rewrite, voltages having polaritiesreverse to each other and reverse to the polarities of the voltages atthe time of writing are applied between both the terminals of the memoryelement to erase information temporarily written into the memory elementand then new information writing is performed.

An electrical conductor containing organic matter, such aspolydiacetylene, TCNQ (tetracyanoquinodimethane), or PEDOT(polyethylenedioxythiophene) is preferably used for the fuse typeelement of the nonvolatile memory elements according to the presentinvention. A conductor containing metal as a main component, such asgold, aluminum, silver, copper, lead, or indium may be used.

A structure in which a dielectric material is sandwiched by electrodeseach made of a conductor is preferably used for the anti-fuse typeelement of the nonvolatile memory elements according to the presentinvention. A material containing metal or organic matter may be used forthe electrodes. A material containing a metallic oxide or organic mattermay be used as the dielectric material. In particular, a materialcontaining aluminum oxide, tantalum oxide, silicon oxide, a polyimideresin, or an epoxy resin is preferably used.

A structure containing a metallic oxide or organic matter, inparticular, a structure containing copper TCNQ and an aluminum oxidefilm, a structure in which an aluminum thin film is sandwiched byorganic conductors, or the like is preferably used for the rewritabletype element of the nonvolatile memory elements according to the presentinvention.

FIG. 1 shows an equivalent circuit of a memory cell of a semiconductorintegrated circuit according to a preferred embodiment of the presentinvention. This embodiment is an embodiment in which a circuit iscomposed of a p-channel TFT and a fuse type nonvolatile memory element.The p-channel TFT becomes an on state when a negative voltage relativeto a voltage between two main electrodes (one is a source and the otheris a drain) is applied to a gate electrode. In this embodiment, when agate voltage is −24 V, the p-channel TFT becomes a complete on state.The fuse type nonvolatile memory element in this embodiment is anelement using an organic conductor of PEDOT, which is a memory elementhaving a characteristic similar to that of a fuse in which an initialstate is the low impedance state and it is irreversibly changed to thehigh impedance state by applying the predetermined voltage between thetwo terminals.

In FIG. 1, reference numeral 1 denotes a memory cell; 2, a TFT; 3, aword line; 4, a bit line; 5, a base line; 6, a fixed resister; 7 to 9,input terminals; and 10, a memory element.

In the memory cell 1 serving as a fundamental unit of the semiconductorintegrated circuit of the present invention, a gate electrode of theTFT2 is connected with the word line 3, one main electrode thereof isconnected with one terminal of the memory element 10, and the other mainelectrode thereof is connected with the bit line 4. The other terminalof the memory element 10 is connected with the base line 5. The fixedresistor 6 is connected between a connecting point A between the bitline 4 and the other main electrode of the TFT 2 and the input terminal7 of the bit line 4. The circuit includes means for supplying voltageshaving polarities reverse to each other relative to a reference voltageto the input terminal 7 of the bit line 4 and the input terminal 8 ofthe base line 5.

FIG. 2 shows an electrical characteristic of the memory element 10 usedin this embodiment. In FIG. 2, the abscissa indicates a voltage appliedbetween both the terminals of the memory element 10 and the ordinateindicates a current flowing between both the terminals. The initialstate of the memory element 10 is the low impedance state. When thevoltage applied between both the terminals of the memory element 10which is in the initial state gradually rises, as indicated by a solidline in the figure, a current flowing into the memory element 10gradually increases and a current value significantly reduces in thevicinity of 8 V. That is, the low impedance state is changed to the highimpedance state in the vicinity of 8 V serving as a threshold value.With this state, the applied voltage temporarily returns to 0 andgradually rises again. Then, as indicated by a broken line in thefigure, although the current value gradually rises with an increase inapplied voltage, the high impedance state is obtained as compared withthe case of voltage application in the initial state (solid line). Afterthat, such an electrical characteristic is maintained. That is, thememory element 10 acts as the irreversible type nonvolatile memoryelement similar to a fuse.

In the memory element 10, one of the high impedance state and the lowimpedance state is set to “0” and the other is set to “1”. Only in thecase of information corresponding to the low impedance state, a highvoltage of 8 V or more is applied, so that predetermined information canbe written.

FIGS. 3A to 3F are timing charts in information write and readoutoperations of the circuit shown in FIG. 1. In FIGS. 3A to 3F, FIGS. 3Ato 3C show the write operation and FIGS. 3D to 3F show the readoutoperation. FIGS. 3A and 3D each show a voltage Vg applied from the inputterminal 9 to the word line 3. FIGS. 3B and 3E each show a voltage Vaapplied from the input terminal 7 to the bit line 4. FIGS. 3C and 3Feach show a voltage Vb applied from the input terminal 8 to the baseline 5. In this embodiment, the reference voltage is set to 0.

In the write operation, a voltage of −24 V is applied to the word line3, so that the TFT 2 becomes an on state. Next, −24 V is applied fromthe input terminal 7 to the bit line 4 and a voltage of +24 V is appliedfrom the input terminal 8 to the base line 5. Then, a potentialdifference of 48 V is caused between the input terminal 7 of the bitline 4 and the base line 5. When the fixed resistor 6 and the TFT 2which have predetermined resistance values are selected, a potentialdifference of 12 to 15 V is caused between both the terminals of thememory element 10 by voltage drop based on those resistance values. As aresult, the low impedance state which is the initial state of the memoryelement 10 is charged to the high impedance state, so that informationis written.

The application of the high voltage to the memory element 10 is requiredonly in the case where information corresponding to the high impedancestate is written. When information to be written in the memory element10 corresponds to the low impedance state, the voltage applied to thememory element 10 is set to a low value in which the low impedance stateis not changed to the high impedance state.

Next, in the readout operation, a voltage of −24 V is applied to theword line 3 to allow the TFT 2 to be in an on state. Then, −24 V isapplied from the input terminal 7 to the bit line 4. In contrast to thetime of writing, the base line 5 is maintained to be 0 V (grounded).Therefore, a potential difference of 24 V is caused between the inputterminal 7 of the bit line 4 and the base line 5, with the result that acurrent flows therebetween. A potential on the connecting point Abetween the bit line 4 and the other main electrode of the TFT 2 ischanged according to the information stored in the memory element 10,that is, according to whether the memory element 10 is in the highimpedance state or the low impedance state. Thus, the information storedin the memory element 10 can be read out by detecting the potential onthe connecting point A.

In the above-mentioned circuit structure, the resistance value of thefixed resistor 6 is set according to an impedance value of the memoryelement 10 and an on-resistance of the TFT 2 so that a sufficiently highvoltage is applied to only the memory element 10 which is intended tochange to the high impedance state in the write operation and a lowvoltage in which the memory element 10 is not changed from the lowimpedance state to the high impedance state is applied thereto in thereadout operation. The fixed resistor 6 can be used instead of a memberhaving a predetermined resistance, such as a transistor, a wiring, or awiring contact.

In the readout operation, a current may be supplied from a constantcurrent source to the bit line 4. In this case, the fixed resistor 6 canbe omitted.

Means for detecting the potential on the connecting point A is notparticularly limited. For example, a sense amplifier (comparator) ispreferably used.

FIG. 4 shows an equivalent circuit of the semiconductor integratedcircuit according to the embodiment of the present invention using thememory cell shown in FIG. 1. In the figure, reference numerals 11 a to11 d, 21 a to 21 d, 31 a to 31 d, and 41 a to 41 d denote memory cells;13 a to 13 d, word lines; 14 a to 14 d, bit lines; 15 a to 15 d, baselines; 16 a to 16 d, fixed resistors; 17 a to 17 d, 18 a to 18 d, and 19a to 19 d, input terminals; and 20 a to 20 d, sense amplifies.

In this embodiment, the memory cells, each of which has the structureshown in FIG. 1, are arranged in 4 rows and 4 columns. The gateelectrodes of transistors of memory cells in the same row are connectedwith a common word line. The other main electrodes of transistors ofmemory cells in the same column are connected with a common bit line.The other terminals of the memory cells are connected with a common baseline. All the memory cells are wired in matrix by the word lines 13 a to13 d, the bit lines 14 a to 14 d, and the base lines 15 a to 15 d.

In this embodiment, in the write operation, first, the word line 13 a isselected and −24 V is applied from the input terminal 19 a, so that allTFTs of the memory cells 11 a to 11 d connected with the word line 13 abecome an on state. Next, in order that a potential difference betweenthe bit line and the base line may become 48 V with respect to, of thememory cells 11 a to 11 d, only a memory cell whose memory element isintended to change to the high impedance state, −24 V is applied to thebit line and +24 V is applied to the base line. More specifically, −24 Vis applied to the bit line connected with the memory cell which isintended to change to the high impedance state and +24 V is applied tothe base line connected therewith. The bit line and the base line whichare connected with a memory cell whose memory element is intended tomaintain in the low impedance state are maintained to be 0 V.Alternatively, the predetermined voltage is commonly applied to one of agroup including the bit lines 14 a to 14 d and a group including thebase lines 15 a to 15 d. A predetermined voltage is applied to only theother group including the lines connected with the memory cell which isintended to change to the high impedance state. Therefore, the memoryelement of the corresponding memory cell is changed to the highimpedance state.

The above-mentioned operation is repeated for each of the word lines 13b to 13 d, so that information is written in parallel in the pluralitymemory cells for each row.

In the readout operation of information from the integrated circuitshown in FIG. 4, as in the write operation, the word line 13 a isselected to allow the TFT to be in an on state, with the result that −24V is applied to all the bit lines 14 a to 14 d. All the base lines 15 ato 15 d are set to 0 V (grounded). Then, different potentials changedaccording to impedances of the memory elements of the respective memorycells 11 a to 11 d are inputted to sense amplifiers 20 a to 20 d. When−12 V serving as a reference potential (Ref.) is inputted to each of thesense amplifiers 20 a to 20 d and the reference potential is comparedwith the inputted potential from the bit line 14 a, voltagescorresponding to information stored in the respective memory cells 11 aand 11 d are outputted from the sense amplifiers 20 a to 20 d.

The above-mentioned operation is repeated for each of the word lines 13b to 13 d, so that information stored in the plurality of memory cellsis readout in parallel for each row.

In this embodiment, the memory cells are arranged in 4 rows and 4columns and wired in matrix by the word lines, the bit lines, and thebase lines to write and read out information in parallel for each row.However, the present invention is not limited to this. The number ofrows and the number of columns can be freely selected. It is alsopossible to write and read out information in series. In thisembodiment, the sense amplifier is provided for each of the bit lines 14a to 14 d. However, the present invention is not limited to this.Information may be read out in series using a single sense amplifier.

Next, the operation in the case where the reversible type memory cell isused will be described. FIG. 5 shows an equivalent circuit of a memorycell of a semiconductor integrated circuit according to the presentinvention, which is constructed by using a nonvolatile memory element inwhich a coevaporation film made of copper and TCNQ and an extremely thinaluminum oxide film are stacked. In the figure, reference numeral 30denotes a memory element and the same references are provided for thesame members as those shown in FIG. 1.

In the structure shown in FIG. 5, an electrical characteristic from theinitial state is identical to that of the memory cell having thestructure shown in FIG. 1. As shown in FIG. 2, the initial state is thelow impedance state. This state is changed to the high impedance stateby the application of the voltage of about 8 V and then maintained. Asin the structure shown in FIG. 1, −24 V is applied to the bit line 4 and+24 V is applied to the base line 5. Therefore, a high voltage of 8 V ormore can be applied to the memory element 30 to change it to the highimpedance state. When −24 V is applied to the bit line 4, the base line5 is set to 0 V (grounded), and a potential on the connecting point A isdetected, information stored in the memory element 30 can be read out.

In the structure shown in FIG. 5, the information in the memory elementcan be rewritten. More Specifically, a high voltage (that is, −8 V orless) having a polarity reverse to that at a time when the memoryelement 30 is changed to the high impedance state is applied to thememory element 30. Therefore, the information temporarily stored in thememory element 30 is erased and the memory element 30 is returned to theinitial state.

FIGS. 6A to 6C are timing charts at the time of erase operation. FIG. 6Ashows the voltage Vg applied from the input terminal 9 of the word line3. FIG. 6B shows the voltage Va applied from the input terminal 7 of thebit line 4. FIG. 6C shows the voltage Vb applied from the input terminal8 of the base line 5.

As shown in FIGS. 6A to 6C, −24 V is applied to the word line 3 to allowthe TFT 2 to be in an on state. Then, +24 V having a polarity reverse tothat at the time of information writing is applied to the bit line 4 and−24 V having a polarity reverse to that at the time of informationwriting is applied to the base line 5. Therefore, −12 to −15 V having apolarity reverse to that at the time of information writing is appliedbetween both the terminals of the memory element 30, so that the highimpedance state is changed to the low impedance state forinitialization. New information can be written in the initialized memoryelement 30 at the timing shown in FIGS. 3A to 3F.

When the structure shown in FIGS. 6A to 6C is applied to the matrixwiring as shown in FIG. 4, information can be written, read out, anderased in parallel for each row. The number of rows and the number ofcolumns can be freely selected in a like manner. Information may be alsowritten, read out, and erased in series. Efficient rewriting can beperformed by simultaneously erasing on all the memory cells.

According to the present invention, the IC card can be constructed byusing the semiconductor integrated circuit. In the IC card construction,the transistor made of a semiconductor other than single crystallinesilicon can be used for the semiconductor integrated circuit. Thus, thesubstrate such as the glass substrate, the plastic substrate, or thepaper can be used according to its application.

This application claims priority from Japanese Patent Application No.2003-420261 filed on Dec. 18, 2003, which is hereby incorporated byreference herein.

1. A semiconductor integrated circuit comprising: a plurality of memorycells, each of which comprises a field effect transistor having asemiconductor layer bearing a gate electrode and two main electrodes,and having a two-terminal type nonvolatile memory element, wherein oneof the main electrodes of the transistor is connected with one terminalof the nonvolatile memory element, the other main electrode is connectedwith a bit line, the gate electrode is connected with a word line, andthe other terminal of the memory element is connected with a base line;means for detecting a potential on a connecting portion between the bitline and the other main electrode of the transistor; and means capableof supplying voltages having reverse polarities relative to a referencevoltage to an input terminal of the bit line and an input terminal ofthe base line, respectively, wherein the semiconductor layer of thefield effect transistor comprises non-crystalline silicon.
 2. Asemiconductor integrated circuit comprising: a plurality of memorycells, each of which comprises a field effect transistor having asemiconductor layer bearing a gate electrode and two main electrodes,and having a two-terminal type nonvolatile memory element, wherein oneof the main electrodes of the transistor is connected with one terminalof the nonvolatile memory element, the other main electrode is connectedwith a bit line, the gate electrode is connected with a word line, andthe other terminal of the memory element is connected with a base line;means for detecting a potential on a connecting portion between the bitline and the other main electrode of the transistor; and means capableof supplying voltages having reverse polarities relative to a referencevoltage to an input terminal of the bit line and an input terminal ofthe base line, respectively, wherein the semiconductor layer of thefield effect transistor comprises an organic semiconductor.
 3. Asemiconductor integrated circuit, comprising: a plurality of memorycells, each of which comprises a field effect transistor having asemiconductor layer bearing a gate electrode and two main electrodes,and having a two-terminal type nonvolatile memory element, wherein oneof the main electrodes of the transistor is connected with one terminalof the nonvolatile memory element, the other main electrode is connectedwith a bit line, the gate electrode is connected with a word line, andthe other terminal of the memory element is connected with a base line;means for detecting a potential on a connecting portion between the bitline and the other main electrode of the transistor; and means capableof supplying voltages having reverse polarities relative to a referencevoltage to an input terminal of the bit line and an input terminal ofthe base line, respectively, wherein the nonvolatile memory elementcomprises a material containing an organic matter.
 4. A method ofoperating a semiconductor integrated circuit, comprising a plurality ofmemory cells, each of which comprises a field effect transistor having asemiconductor layer bearing a gate electrode and two main electrodes,and having a two-terminal type nonvolatile memory element, wherein oneof the main electrodes of the transistor is connected with one terminalof the nonvolatile memory element, the other main electrodes isconnected with a bit line, the gate electrode is connected with a wordline, and the other terminal of the memory element is connected with abase line; and means for detecting a potential on a connecting portionbetween the bit line and the other main electrodes of the transistor,the method comprising: supplying voltages having reverse polaritiesrelative to a reference voltage to an input terminal of the bit line andan input terminal of the base line, respectively, to apply apredetermined voltage between both terminals of the memory element,wherein the nonvolatile memory element comprises a rewritable memoryelement, and a predetermined voltage is applied between both terminalsof the memory element to write information therein by supplying thevoltages having reverse polarities relative to the reference voltage tothe input terminal of the bit line and the input terminal of the baseline, respectively; and a predetermined voltage having a polarityreverse to that of a writing voltage is applied between both theterminals of the memory element to erase the information written in thememory element.